The present invention relates to a semiconductor integrated circuit device including a dynamic random access memory (hereafter, it is called DRAM), and to a dummy word line drive system of the DRAM, for example.
Traditionally, as techniques related to memories, there are those described in documents such as JP-A-60-242591 or JP-A-6-187781. FIG. 9 is a schematic circuit diagram illustrating an exemplary configuration of a memory cell part in a DRAM described in JP-A-6-187781 (hereafter, it is simply called Document 2). The memory cell part was proposed for solving disadvantages of the memory cell part described in JP-A-60-242591 (hereafter, it is simply called Document 1), in which complementary first and second bit lines BLa and BLb, a plurality of word lines WL0 and WL1 intersecting each of the bit lines BLa and BLb, a plurality of first dummy word lines DWL0 and DWL1 intersecting the bit lines BLa and BLb, and a plurality of second dummy word lines DWL2 and DWL3 arranged close to the first dummy word lines DWL0 and DWL1 nearly in parallel therewith are provided.
A dynamic memory cell 100 is connected at the intersection of the bit line BLb and the word line WL0, and a dynamic memory cell 101 is connected at the intersection of the bit line BLa and the word line WL1. Each of the memory cells 100 and 101 has a charge storage capacitor 11 and a charge transfer N-channel MOS transistor (hereafter, it is called NMOS) 12. They are serially connected between ½·VCC and the bit lines BLb and BLa (where VCC is power supply voltage).
Dummy cells 200 and 201 are connected at the intersections of the bit lines BLb and BLa and the dummy word lines DWL0 and DWL1, respectively, and dummy cells 202 and 203 are connected at the intersections of the bit lines BLa and BLb and the dummy word lines DWL2 and DWL3, respectively. Each of the dummy cells 200 to 203 is configured of an NMOS.
An equalizer circuit 30 for equalizing the bit lines BLa and BLb to ½·VCC is connected to one ends of the bit lines BLa and BLb. The equalizer circuit 30 is configured of an NMOS 31 connected between the bit line BLa and ½·VCC, an NMOS 32 connected between the bit line BLb and ½·VCC, and an NMOS 33 connected between the bit lines BLa and BLb, and the NMOSs are turned on/off by an equalizer signal EQ.
To the other ends of the bit lines BLa and BLb, a sense amplifier 40 for sensing and amplifying potential difference between the bit lines BLa and BLb is connected, and complementary data lines Da and Db are connected through data transfer NMOSs 51 and 52 to be turned on/off by a column line Y-DEC. The sense amplifier 40 is configured of NMOSs 41 and 42 and P-channel MOS transistors (hereafter, called PMOS) 43 and 44, which are cross connected between the bit lines BLa and BLb in which the NMOSs 41 and 42 are turned on/off by an activating signal φa and the PMOSs 43 and 44 are turned on/off by an activating signal φb in the opposite phase of the activating signal φa.
In the memory cell part of Document 1, the second dummy word lines DWL2 and DWL3 and the dummy cells 202 and 203 are omitted. In such the memory cell part, the readout operation of information 0 stored in the memory cell 100, for example, will be described.
When the equalizer signal EQ is at the VCC level, the bit lines BLa and BLb are equalized to ½·VCC because the NMOSs 31, 32 and 33 in the equalizer circuit 30 are in the ON state. In addition, the sense amplifier activating signals φa and φb are also equalized to ½·VCC. When the equalizer signal EQ falls from the VCC level to a ground voltage (hereafter, it is called GND) level, the NMOSs 31 to 33 in the equalizer circuit 30 are turned to the OFF state. Then, the word line WL0 selected by a decoder, not shown, rises to turn on the NMOS 12 in the memory cell 100, and information 0 stored in the capacitor 11 is outputted to the bit line BLb. At this time, the word line WL0 rises from the GND level to a (VCC+Vt+α) level (where Vt is the threshold voltage of the NMOS), and the dummy word line DWL0 falls from the VCC level to the GND level. The dummy word line DWL1 remains at the VCC level.
Subsequently, the sense amplifier activating signal φa gradually rises from the ½·VCC level to the VCC level, and the sense amplifier activating signal φb falls from the ½·VCC level to the GND level. Then, the sense amplifier 40 operates to amplify the bit line BLa to the VCC level and the bit line BLb to the GND level. After that, the column line Y-DEC rises from the GND level to the VCC level, the data transfer NMOSs 51 and 52 are turned to the ON state, and information of the bit lines BLa and BLb is transferred to the data lines Da and Db.
By disposing the dummy cells 200 and 201, which are originally unnecessary, the memory cell part of the half precharge system described in Document 1 has advantages that can avoid unbalance in the bit line to potential caused by combined voltage of the word lines WL0 and WL1 with the bit lines BLa and BLb and that can increase operational margins to prevent malfunctions.
However, when the word line WL0 is changed from the GND level to the (VCC+Vt+α) level and the dummy word line DWL0 is changed from the VCC level to the GND level in information readout from the memory cell 100, the capacitive coupling of gate capacitances between the word line WL0 and the bit line BLb and between the dummy word line DWL0 and the bit line BLb generates the offset voltage ΔVs between the bit lines BLa and BLb because of the presence of the difference in voltage amplitude ΔV=Vt+α. On this account, there is a disadvantage that a loss is generated in the amount of a readout signal to cause the sense amplifier 40 to malfunction.
Furthermore, when voltage is turned to VCC=1.5 V in a DRAM using voltage level lower than VCC=3.3 V used for a 16-Mbit DRAM, there is a disadvantage that a loss is further increased in the amount of the readout signal because a rate of (Vt+α) occupied in the activation level of the word lines WL0 and WL1 is further up.
Then, in order to solve the disadvantages, a plurality of second dummy word lines DWL2 and DWL3 and a plurality of dummy cells 202 and 203 are disposed near a plurality of first dummy word lines DWL0 and DWL1 in the memory cell part of Document 2.
In the memory cell part of Document 2, when information 0 stored in the memory cell 100 is read out where the boost levels of the word lines WL0 and WL1 are (VCC+Vt+α), for example, the word line WL0 is changed from the GND level to the (VCC+vt+α) level. At this time, the first dummy word line DWL0 is changed from the VCC level to the GND level, and the second dummy word line DWL2 is changed from the VCC level to the (VCC+Vt+α) level. Therefore, the offset voltage ΔVs generated between the bit lines BLa and BLb is cancelled to be zero. Accordingly, the amount of the signal transmitted from the memory cell 100 to the bit line BLb is not varied, and correct information can be read out. In addition to this, since the offset voltage ΔVs generated between the bit lines BLa and BLb is zero, a loss is not generated in the amount of the readout signal and correct information can be read out even in the case of a DRAM using low voltage VCC=1.5 V, for example.
However, although the semiconductor integrated circuit device described in Document 2 can solve the disadvantages of the semiconductor integrated circuit device in Document 1, it needs to be added with the plurality of the second dummy word lines DWL2 and DWL3 and the plurality of the dummy cells 202 and 203. Thus, drive circuits for driving the added dummy word lines DWL2 and DWL3 need to be disposed, and then the number of the circuit elements is increased. Furthermore, since the second the dummy word lines DWL2 and DWL3 are disposed over some of the array configurations, the area for forming the dummy word lines is increased. On this account, there are problems that the chip size is scaled up and the amount of power consumption is increased because the dummy word lines DWL2 and DWL3 are driven, and the problems are difficult to solve.